Electrostatic discharge (ESD) and electrical overstress (EOS) are two of the most dominant reliability concerns in the semiconductor industry. The failure susceptibility of integrated circuits (ICs) to ESD and EOS increases as the IC technology progresses towards submicron feature lengths. In spite of the fact that EOS embodies a broad category of electrical threats to semiconductor devices, it is generally accepted that EOS stress sources cause device failure as a result of device self-heating and furthermore, that these sources can be modeled as current sources. This being the case, EOS/EOS immunity of integrated circuits may be qualified in terms of the stress power and/or the stress current required to induce device failure in a specified time.
ESD protection for input, output and/or power supply pins in advanced CMOS ICs is achieved by a protection network that shunts the protected pin and the ground bus under stress events. For input pins, a dedicated protection network that is completely passive under normal operating conditions is added to the input's functional circuitry. For output pins, protection against ESD and EOS is attained with a dedicated protection network whose failure thresholds can in some cases be enhanced by the self-protection capability of the output buffer transistors.
The most common protection schemes used in MOS ICs rely on the parasitic bipolar transistor associated with a nMOS device whose drain is connected to the pin to be protected and whose source tied to ground. The protection level or failure threshold can be set by varying the nMOS device width. Under stress conditions, the dominant current conduction path between the protected pin and ground involves the parasitic bipolar transistor of that nMOS device. This parasitic bipolar transistor operates in the snapback region under pin positive with respect to ground stress events.
The dominant failure mechanism found in the nMOS protection device operating in snapback conditions is the onset of second breakdown. Second breakdown is a phenomena that induces thermal runaway in the device wherever the reduction of the impact ionization current is offset by the thermal generation of carriers. Second breakdown is initiated in a device under stress as a result of the self-heating. The peak nMOS device temperature at which second breakdown is initiated is known to increase with the stress current level. The time required for the structure to heat-up to this critical temperature is dependent on the device layout and stress power distribution across the device. Furthermore, the peak temperature is proportional to the power density. In nMOS protection transistors, power dissipation is confined to a volume given by EQU .DELTA.=W.multidot.Xj.multidot.W.sub.D.sbsb.--.sub.dep
where W is the device width, Xj is the drain junction depth, and W.sub.D.sbsb.--.sub.dep (.apprxeq.0.1 .mu.m) is the width of the drain depletion region near the gate edge. According to this expression for .DELTA., the power density is reduced through design by increasing the nMOS device width W.